Double-sampling Σ∆ Adc’s with Bilinear Integrators

Double-sampling allows to double the sampling frequency of a Σ∆ ADC without increasing the clock frequency. Unfortunately, path mismatch between the double-sampling branches causes noise folding, which ruins the performance. The fully-floating integrator is an interesting circuit to be used in such a double-sampling Σ∆ ADC because it is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect, which effectively increases the order of the modulator by one. Due to this, previously presented structures don’t have enough freedom to fully control the modulator pole positions. In this work we introduce modified topologies for double-sampling Σ∆-modulators with bilinear integrators. We show that these architectures provide full control of the modulator poles and hence can be used to implement any noise transfer function.